It is more difficult to migrate from large nodes, such as from 16nm to 7Nm. He said that this needs to be transformed from a double pattern to a computing design platform with completely different rules. All of these are embodied in the network chip, and the network chip (NoC) acts as a coupling logic device between CPU, cache, accelerator and memory.

"Silicon enables us to integrate more functionality on the same chip, but from a design point of view, you can still call a network chip a IP module because SoC designers can use the NoC as a build module without further understanding of its implementation details," said Winefeld. It makes no sense to harden this IP as long as it follows these protocols, logically, and meets the requirements of these high level systems, such as delay, bandwidth, and quality of service. As you can imagine, this NoC is located in the channel between the IP connected to it, these IP can be hard or soft. The NoC used for connection purposes is soft, and the topology and layout of NoC are very different. For the SoC used, it is specific.

Making IP blocks work together is only one aspect of the problem. It is another matter to verify these IP in the functional test chip.

"If you are a IP provider, you need to finish the functional test chip on all the smaller size process nodes, because people will ask that," said Ranjit Adhikary, vice president of marketing at ClioSoft. "They are not very concerned about whether this is a hard core or a soft core. What they want to know is whether you have completed the functional test chip. Because of the high cost of one-off projects, this matter is quite challenging. For a small company, if you can not guarantee that you can get many orders, it will be very difficult to invest on test chips. If you are a system company and are using your own IP, the money will be meaningful. But you still need to think about how much it will cost to do a functional test chip and how much effort it will take, because the cost of moving IP to a high-level node is very expensive. "

In addition, there is more validation.

John Ferguson, SIEMENS's Mentor product marketing director, said: "there must be a lot of extra validation, and a real check on the impact of each small problem to avoid blind neglect. I think it also means more early trial and error to ensure the final success. We once thought and hoped that with EUV lithography technology, things would get better or easier, but it turned out that we were too optimistic. EUV may make things easier at one or two levels, but not the whole. There are so many interdependence between the plates that it will not help at all. Some people say, 'look, it's a lot of benefits', but when you really understand it, there's no free lunch in the world, and you have to take something else for the benefits.

A possible solution to all of these problems has attracted the attention of advanced technology chip designers, mainly involving more mixing and matching of IP and blocks that will be developed on different process nodes.

Anush Mohandass, vice president of NetSpeed Systems market and business development, points out that heterogeneity is driving new ideas about SoC design.

"One trend here is the concept of multi-layer chips, in which the basic layer may contain I / O and some peripherals designed on the 28nm process. The various computing components for performance improvement are placed on a separate layer, perhaps 16nm or 7Nm," Mohandass said. "These layers need some form of intelligent linking."

"Logically speaking, this may be a large SoC, but you can partition it," Mohandass pointed out. "Even if there is a standard IP, we can look at it from the perspective of divide and rule. They said, 'this is my CPU subsystem, this is my image subsystem, this is my memory subsystem,' you divide the design with different subsystems, and then integrate them together. The situation we are seeing is very similar. In addition to the existence of these subsystems on separate chips, the concept remains the same. We just put these subsystems in the same package. Obviously, there is a need for a rather complex interconnection, but this kind of multi-layer chip is becoming more and more popular on more sophisticated process nodes.

Of course, some problems have not disappeared, such as layer planning. Moreover, although the speed of node upgrading is faster and faster, the development time of some advanced process components is getting longer and longer.

Mark Richards, the technology marketing manager of Synopsys's physical implementation department, said: "in the whole process, the layout of this step appears earlier. You still have to design from V0.1 or v0.5, and the whole design process becomes longer. In process development, more interaction with leading customers is needed to facilitate all things smoothly. However, the speed of updating nodes and the speed of the introduction of half nodes make the work more difficult.

From the point of the wafer fabrication plant, the chip's part of the logic device is zoomed, and the other is kept on the same process node, which can make the half node crawl faster. Whether this can make the work of IP developers easier, is not yet fully understood, but it seems to be an attractive option. "If you just want to use this in exactly the same way as before, in the new design.